View LTC4213CDDB_1203736.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc4213 1 4213f applicatio s u typical applicatio u descriptio u features the ltc ? 4213 is an electronic circuit breaker. an over- current circuit breaker senses the voltage across the drain and source terminals of an external n-channel mosfet with no need for a sense resistor. the advantages are a lower cost and reduced voltage and power loss in the switch path. an internal high-side driver controls the external mosfet gate. two integrated comparators provide dual level over- current protection over the bias supply to ground common mode range. the slow comparator has 16 s response while the fast comparator trips in 1 s. the circuit breaker has three selectable trip thresholds: 25mv, 50mv and 100mv. an on pin controls the on/off and resets circuit breaker faults. ready signals the mosfet is conducting and the circuit breaker is armed. the ltc4213 operates from v cc = 2.3v to 6v. electronic circuit breaker high-side switch hot board insertion fast 1 s response circuit breaker 3 selectable circuit breaker thresholds no sense resistor required dual level overcurrent fault protection controls load voltages from 0v to 6v high side drive for external n-channel fet undervoltage lockout ready pin signals when circuit breaker armed small plastic (3mm x 2mm) dfn package no r sense electronic circuit breaker 1.25v electronic circuit breaker off on ltc4213 v cc on ready 10k i sel gnd gate si4864dy v bias v out 1.25v 3.5a v in 1.25v v bias 2.3v to 6v sensen sensep 4213 ta01 , ltc and lt are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. severe overload response 2 s/div 4213 ta01b i out (50a/div) v gate (5v/div) v out (1v/div) v in (1v/div)
ltc4213 2 4213f bias supply voltage (v cc ) ........................... C0.3v to 9v input voltages on, sensep, sensen .............................C 0.3v to 9v i sel .......................................... C 0.3v to (v cc + 0.3v) output voltages gate .....................................................C 0.3v to 15v ready .....................................................C 0.3v to 9v operating temperature range ltc4213c ............................................... 0 c to 70 c ltc4213i ............................................. C40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10sec)................... 300 c order part number ddb part* marking t jmax = 125 c, ja = 250 c/w exposed pad (pin 9) pcb connection optional consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. lbhv LTC4213CDDB ltc4213iddb absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, i sel = 0 unless otherwise noted. (note 2) symbol parameter conditions min typ max units v cc bias supply voltage 2.3 6 v v sensep sensep voltage 06v i cc v cc supply current 1.6 3 ma v cc(uvlr) v cc undervoltage lockout release v cc rising 1.8 2.07 2.23 v ? v cc(uvhyst) v cc undervoltage lockout hysteresis 30 100 160 mv i sensep sensep input current v sensep = v sensen = 5v, normal mode 15 40 80 a v sensep = v sensen = 0, normal mode C1 15 a i sensen sensen input current v sensep = v sensen = 5v, normal mode 15 40 80 a v sensep = v sensen = 0, normal mode C1 15 a v sensep = v sensen = 5v, 50 280 a reset mode or fault mode v cb circuit breaker trip voltage i sel = 0, v sensep = v cc 22.5 25 27.5 mv v cb = v sensep C v sensen i sel = floated, v sensep = v cc 45 50 55 mv i sel = v cc, v sensep = v cc 90 100 110 mv v cb(fast) fast circuit breaker trip voltage i sel = 0, v sensep = v cc 63 100 115 mv v cb(fast) = v sensep C v sensen i sel = floated, v sensep = v cc 126 175 200 mv i sel = v cc, v sensep = v cc 252 325 371 mv i gate(up) gate pin pull up current v gate = 0v C50 C100 C150 a i gate(dn) gate pin pull down current ? v sensep C v sensen = 200mv, v gate = 8v 10 40 ma ? v gsmax external n-channel gate drive v sensen = 0, v cc 2.97v, i gate = C1 a 4.8 6.5 8 v v sensen = 0, v cc = 2.3v, i gate = C1 a 2.65 4.3 8 v ? v gsarm v gs voltage to arm circuit breaker v sensen = 0, v cc 2.97v 4.4 5.4 7.6 v v sensen = 0, v cc = 2.3v 2.5 3.5 7 v top view ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 9 4 3 2 1 ready on i sel gnd v cc sensep sensen gate
ltc4213 3 4213f ? v gsmax C ? v gsarm difference between ? v gsmax and v sensen = 0, v cc 2.97v 0.3 1.1 v ? v gsarm v sensen = 0, v cc = 2.3v 0.15 0.8 v v ready(ol) ready pin output low voltage i ready = 1.6ma, pull down device on 0.2 0.4 v i ready(leak) ready pin leakage current v ready = 5v, pull down device off 0 1 a v on(th) on pin high threshold on rising, gate pulls up 0.76 0.8 0.84 v ? v on(hyst) on pin hysteresis on falling, gate pulls down 10 40 90 mv v on(rst) on pin reset threshold on falling, fault reset, gate pull down 0.36 0.4 0.44 v i on(in) on pin input current v on = 1.2v 0 1 a ? v ov overvoltage threshold 0.41 0.7 1.1 v ? v ov = v sensep C v cc t ov overvoltage protection trip time v sensep = v sensen = step 5v to 6.2v 25 65 160 s t fault(slow) v cb trips to gate discharging ? v sense step 0mv to 50mv, 71627 s v sensen falling, v cc = v sensep = 5v t fault(fast) v cb(fast) trips to gate discharging ? v sense step 0v to 0.3v, v sensen falling, 1 2.5 s v sensep = 5v t debounce startup de-bounce time v on = 0v to 2v step to gate rising, 27 60 130 s (exiting reset mode) t ready ready delay time v gate = 0v to 8v step to ready rising, 22 50 115 s v sensep = v sensen = 0 t off turn-off time v on = 2v to 0.6v step to gate discharging 1.5 5 10 s t on turn-on time v on = 0.6v to 2v step to gate rising, 4 8 16 s (normal mode) t reset reset time v on step 2v to 0v 20 80 150 s note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, i sel = 0 unless otherwise noted. (note 2) symbol parameter conditions min typ max units note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified.
ltc4213 4 4213f i cc vs v cc i cc vs temperature v cc(uvlr) vs temperature normalized v cb vs v cc normalized v cb vs temperature normalized v cb(fast) vs v cc normalized v cb(fast) vs temperature i gate(up) vs v cc i gate(up) vs temperature typical perfor a ce characteristics uw specifications are at t a = 25 c. v cc = 5v unless otherwise noted. bias supply voltage (v) 2.0 0 bias supply current (ma) 0.5 1.0 1.5 2.0 3.0 4.0 5.0 6.0 4213 g01 2.5 3.0 2.5 3.5 4.5 5.5 temperature ( c) C50 0 bias supply current (ma) 0.5 1.0 1.5 2.0 050 100 125 4213 g02 2.5 3.0 C25 25 75 temperature ( c) C50 1.7 undervoltage lockout threshold (v) 1.8 1.9 2.0 2.1 050 100 125 4213 g03 2.2 2.3 C25 25 75 v cc rising v cc falling bias supply voltage (v) 2.0 0.94 normalized v cb 0.96 0.98 1.00 1.02 3.0 4.0 5.0 6.0 4213 g04 1.04 1.06 2.5 3.5 4.5 5.5 temperature ( c) C50 0 50 100 125 4213 g05 C25 25 75 0.94 normalized v cb 0.96 0.98 1.00 1.02 1.04 1.06 bias supply voltage (v) 2.0 3.0 4.0 5.0 6.0 4213 g06 2.5 3.5 4.5 5.5 0.94 normalized v cb(fast) 0.96 0.98 1.00 1.02 1.04 1.06 temperature ( c) C50 0 50 100 125 4213 g07 C25 25 75 0.94 normalized v cb(fast) 0.96 0.98 1.00 1.02 1.04 1.06 bias supply voltage (v) 2.0 96 i gate(up) ( a) 98 100 102 3.0 4.0 5.0 6.0 4213 g08 104 2.5 3.5 4.5 5.5 temperature ( c) C50 0 50 100 125 C25 25 75 96 i gate(up) ( a) 98 100 102 4213 g09 104
ltc4213 5 4213f typical perfor a ce characteristics uw ? v gsmax and ? v gsarm vs v cc ? v gsmax and ? v gsarm vs temperature v on(th) vs v cc v on(th) vs temperature ? v ov vs v cc ? v ov vs temperature t debounce and t ready vs v cc t debounce and t ready vs temperature t reset vs v cc specifications are at t a = 25 c. v cc = 5v unless otherwise noted. bias supply voltage (v) 2.0 3 ? v gsmax and ? v gsarm (v) 5 4 6 7 3.0 4.0 5.0 6.0 4213 g10 8 2.5 3.5 4.5 5.5 ? v gsmax ? v gsarm 3 ? v gsmax and ? v gsarm (v) 5 4 6 7 4213 g11 8 temperature ( c) C50 0 50 100 125 C25 25 75 ? v gsmax (for 2.5v cc ) ? v gsarm (for 2.5v cc ) ? v gsmax (for 5v cc ) ? v gsarm (for 5v cc ) bias supply voltage (v) 2.0 3.0 4.0 5.0 6.0 4213 g12 2.5 3.5 4.5 5.5 0.65 0.70 on pin threshold (v) 0.75 0.80 0.85 0.90 low threshold high threshold bias supply voltage (v) 2.0 t debounce and t ready ( s) 3.0 4.0 5.0 6.0 2.5 3.5 4.5 5.5 0 20 40 60 4213 g16 80 100 t debounce t ready bias supply voltage (v) 2.0 0 t reset ( s) 40 20 60 80 3.0 4.0 5.0 6.0 4213 g18 100 120 2.5 3.5 4.5 5.5 temperature ( c) C50 0 50 100 125 4213 g13 C25 25 75 0.65 0.70 on pin threshold (v) 0.75 0.80 0.85 0.90 low threshold high threshold bias supply voltage (v) 2.0 3.0 4.0 5.0 6.0 4213 g14 2.5 3.5 4.5 5.5 0.66 overvoltage threshold (v) 0.68 0.70 0.72 0.74 4213 g15 0.4 0.6 0.5 overvoltage threshold (v) 0.7 0.8 0.9 1.0 temperature ( c) C50 0 50 100 125 C25 25 75 temperature ( c) C50 0 50 100 125 C25 25 75 t debounce and t ready ( s) 0 20 40 60 4213 g17 80 100 t debounce t ready
ltc4213 6 4213f t reset vs temperature t fault(slow) vs v cc t fault(slow) vs temperature t fault(fast) vs v cc t fault(fast) vs temperature typical perfor a ce characteristics uw specifications are at t a = 25 c. v cc = 5v unless otherwise noted. t fault(fast) ( s) 4213 g23 0.9 0.8 0.7 1.0 1.1 1.2 1.3 temperature ( c) C50 0 50 100 125 C25 25 75 bias supply voltage (v) 2.0 10 t fault(slow) ( s) 14 12 16 18 3.0 4.0 5.0 6.0 4213 g20 20 22 2.5 3.5 4.5 5.5 temperature ( c) C50 0 50 100 125 4213 g21 C25 25 75 10 t fault(slow) ( s) 14 12 16 18 20 22 temperature ( c) C50 0 50 100 125 4213 g19 C25 25 75 t reset ( s) 60 70 80 90 100 bias supply voltage (v) 2.0 t fault(fast) ( s) 3.0 4.0 5.0 6.0 4213 g22 2.5 3.5 4.5 5.5 0.9 0.8 0.7 1.0 1.1 1.2 1.3
ltc4213 7 4213f pi fu ctio s uuu ready (pin 1): ready status output. open drain output that goes high impedance when the external mosfet is on and the circuit breaker is armed. otherwise this pin pulls low. on (pin 2): on control input. the ltc4213 is in reset mode when the on pin is below 0.4v. when the on pin increases above 0.8v, the device starts up and the gate pulls up with a 100 a current source. when the on pin drops below 0.76v, the gate pulls down. to reset a circuit breaker fault, the on pin must go below 0.4v. i sel (pin 3): threshold select input. with the i sel pin grounded, float or tied to v cc the v cb is set to 25mv, 50mv or 100mv, respectively. the corresponding v cb(fast) values are 100mv, 175mv and 325mv. gnd (pin 4): device ground. gate (pin 5): gate drive output. an internal charge pump supplies 100 a pull-up current to the gate of the external n-channel mosfet. internal circuitry limits the voltage between the gate and sensen pins to a safe gate drive voltage of less than 8v. when the circuit breaker trips, the gate pin abruptly pulls to gnd. sensen (pin 6): circuit breaker negative sense input. connect this pin to the source of the external mosfet. during reset or fault mode, the sensen pin discharges the output to ground with 280 a. sensep (pin 7): circuit breaker positive sense input. connect this pin to the drain of external n-channel mosfet. the circuit breaker trips when the voltage across sensep and sensen exceeds v cb . the input common mode range of the circuit breaker is from ground to v cc + 0.2v when v cc < 2.5v. for v cc 2.5v, the input common mode range is from ground to v cc + 0.4v. v cc (pin 8): bias supply voltage input. normal operation is between 2.3v and 6v. an internal under-voltage lockout circuit disables the device when v cc < 2.07v. exposed pad (pin 9): exposed pad may be left open or connected to device ground.
ltc4213 8 4213f block diagra w v cc v cb 0.7v v cb(fast) 4213 bd i sel ready gate on gnd v cc sensen sensep 4 2 7 6 8 5 3 1 C + + C +C sensen gateoff reset startup normal mode gate on/off 6.5v clamp circuit charge pump v cb 100mv 50mv 25mv v cb(fast) 325mv 175mv 100mv v gsarm arm comp C + comp1 arm 0.4v logic C + slowcomp + C uv comp v cc 2.07v + C comp2 0.8v 80 s delay 16 s delay 50 s delay 60 s delay 8 s 5 s cb trips + C C + fastcomp 1 s delay cb trips blank reset or fault mode 280 a 100 a + C C + ovcomp 65 s delay ov trips gate on v cc delay
ltc4213 9 4213f ti i g diagra w u w 0.3v 1.2v 0.3v 0.3v v on(th) v on(rst) 12 34 56 12 3 4 5 v on v on(th) v on(th) C v on(hyst) v on(th) v gsmax v gsmax C 0.3v v gsmax v gsmax C 0.3v v gate ? v sense v on v gate t debounce t off t on t fault(fast) t reset 4213 td
ltc4213 10 4213f applicatio s i for atio wu u u figure 1 shows an electronic circuit breaker (ecb) appli- cation. an external auxiliary supply biases the v cc pin and the internal circuitry. a v in load supply powers the load via an external mosfet. the sensep and sensen pins operatio u overview the ltc4213 is an electronic circuit breaker (ecb) that senses load current with the the r dson of the external mosfet instead of using an external sense resistor. this no r sense method is less precise than r sense method due to the variation of r dson . however, the advantages are less complex, lower cost and reduce voltage and power loss in the switch path owing to the absence of a sense resistor. without the external sense resistor voltage drop, the v out improvement can be quite significant especially in the low voltage applications. the ltc4213 is designed to operate over a bias supply range from 2.3v to 6v. when bias supply voltage and the on pin are sufficiently high, the gate pin starts charging after an internal debounce delay of 60 s. during the gate ramp-up, the circuit breaker is not armed until the external mosfet is fully turned on. once the circuit breaker is armed, the ltc4213 monitors the load current through the r dson of the external mosfet. circuit breaker function the ltc4213 provides dual level and dual response time circuit breaker functions for overcurrent protection. the ltc4213 circuit breaker function block consists of two comparators, slowcomp and fastcomp. the thresholds of slowcomp and fastcomp are v cb and v cb(fast) . the i sel pin selects one of the three settings: 1. v cb = 25mv and v cb(fast) = 100mv with i sel at gnd 2. v cb = 50mv and v cb(fast) = 175mv with i sel floating 3. v cb = 100mv and v cb(fast) = 325mv with i sel at v cc i sel can be stepped dynamically, such as to allow a higher circuit breaker threshold at startup and a lower threshold after supply current has settled. the inputs of the com- parators are sensep and sensen pins. the voltage across the drain and source of the external mosfet is sensed at sensep and sensen. ? vv v sense sensep sensen = ? () 1 when ? v sense exceeds the v cb threshold but is less than v cb(fast) , the comparator slowcomp trips the circuit breaker after a 16 s delay. if ? v sense is greater than v cb(fast) , the comparator fastcomp trips the circuit breaker in 1 s. a severe short circuit condition can cause the load supply to dip substantially. this does not pose a problem for the ltc4213 as the input stages of the current limit compara- tors are common mode to ground. sense the load current at the drain and source of the external mosfet. in ecb applications, large input bypass capacitors are usually recommended for good transient performance. undervoltage lockout an internal undervoltage lockout (uvlo) circuit resets the ltc4213 if the v cc supply is too low for normal operation. the uvlo comparator (uvcomp) has a low-to-high thresh- old of 2.07v and 100mv of hysteresis. uvlo shares the glitch filters for both low-to-high transition (startup) and high-to-low transition (reset) with the on pin compara- tors. above 2.07v bias supply voltage, the ltc4213 starts if the on pin conditions are met. short, shallow bus bias 4213 f01 + ltc4213 v cc on ready c1 0.1 f c load 100 f r4 10k i sel gnd gate q1 si4864dy v cc v out 1.25v 3.5a sensen sensep v bias 2.5v v in 1.25v + c in 100 f off on figure 1. ltc4213 electronic circuit breaker application
ltc4213 11 4213f supply transient dips below 1.97v of less than 80 s are ignored. on function when v on is below comparator comp1s threshold of 0.4v for 80 s, the device resets. the system leaves reset mode if the on pin rises above comparator comp2s threshold of 0.8v and the uvlo condition is met. leaving reset mode, the gate pin starts up after a t debounce delay of 60 s. when on goes below 0.76v, the gate shuts off after a 5 s glitch filter delay. the output is discharged by the external load when v on is in between 0.4v to 0.8v. at this state, the on pin can re-enable the gate if v on exceeds 0.8v for more than 8 s. alternatively, the device resets if the on pin is brought below 0.4v for 80 s. once reset, the gate pin restarts only after the t debounce 60 s delay at v on rising above 0.8v. to protect the on pin from overvoltage stress due to supply transients, a series resistor of greater than 10k is recommended when the on pin is connected directly to the supply. an external resis- tive divider at the on pin can be used with comp2 to set a supply undervoltage lockout value higher than the inter- nal uvlo circuit. an rc filter can be implemented at the on pin to increase the powerup delay time beyond the internal 60 s delay. gate function the gate pin is held low in reset mode. 60 s after leaving reset mode, the gate pin is charged up by an internal 100 a current source. the circuit breaker arms when v gate > v sensen + ? v gsarm . in normal mode operation, the gate peak voltage is internally clamped to ? v gsmax above the sensen pin. when the circuit breaker trips, an internal mosfet shorts the gate pin to gnd, turning off the external mosfet. ready status the ready pin is held low during reset and at startup. it is pulled high by an external pullup resistor 50 s after the circuit breaker arms. the ready pin pulls low if the circuit breaker trips or the on pin is pulled below 0.76v, or v cc drops below undervoltage lockout. ? v gsarm and v gsmax each mosfet has a recommended v gs drive voltage where the channel is deemed fully enhanced and r dson is minimized. driving beyond this recommended v gs volt- age yields a marginal decrease in r dson . at startup, the gate voltage starts at ground potential. the gate ramps past the mosfet threshold and the load current begins to flow. when v gs exceeds ? v gsarm , the circuit breaker is armed and enabled. the chosen mosfet should have a recommended minimum v gs drive level that is lower than ? v gsarm . finally, v gs reaches a maximum at ? v gsmax. trip and reset circuit breaker figure 2 shows the timing diagram of v gate and v ready after a fault condition. a tripped circuit breaker can be reset either by cycling the v cc bias supply below uvlo thresh- old or pulling on below 0.4v for >t reset . figure 3 shows the timing diagram for a tripped circuit breaker being reset by the on pin. calculating current limit the fault current limit is determined by the r dson of the mosfet and the circuit breaker voltage v cb . i v r limit cb dson = () 2 the r dson value depends on the manufacturers distribu- tion, v gs and junction temperature. short kelvin-sense connections between the mosfet drain and source to the ltc4213 sensep and sensen pins are strongly recommended. for a selected mosfet, the nominal load limit current is given by: i v r limit nom cb nom dson nom () () () () = 3 the minimum load limit current is given by: i v r limit min cb min dson max () () () () = 4 applicatio s i for atio wu u u
ltc4213 12 4213f applicatio s i for atio wu u u figure 2. short circuit fault timing diagram ab cb trips ? v sense v gate v cb >v cb v ready circuit breaker trips gate and ready pins pull low short circuit t fault 4213 f02 the maximum load limit current is given by: i v r limit max cb max dson min () () () () = 5 most mosfet data sheets have an r dson specification with typical and maximum values but no minimum value. assuming a normal distribution with typical as mean, the minimum value can be estimated as rrr dson min dson nom dson max () ( ) ( ) () =? ? 26 the ltc4213 gives higher gate drive than the manufac- turer specified gate drive for r dson . this gives a slightly lower r dson than specified. operating temperature also modulates the r dson value. example current limit calculation an si4410dy is used for current detection in a 5v supply system with the ltc4213 v cb at 25mv (i sel pin grounded). the r dson distribution for the si4410dy is typical r dson = 0.015 ? = 100% maximum r dson = 0.02 ? = 133.3% estimated min r dson = 2 ? 15 C 20 = 0.010 ? = 66.7% the r dson variation due to gate drive is r dson @ 4.5v gs = 0.015 ? = 100% (spec. typ) r dson @ 4.8v gs = 0.014 ? = 93% (min ? v gsmax ) r dson @ 7v gs = 0.0123 ? = 82% (nom ? v gsmax ) r dson @ 8v gs = 0.012 ? = 80% (max ? v gsmax )
ltc4213 13 4213f applicatio s i for atio wu u u figure 3. resetting fault timing diagram v cb 12 3 4 5 6 7 8 restart v ready v gate normal mode startup cycle v on < 0.4v duration > t reset t fault t debounce fault latched off v cc > 2.07v ? v sense 4213 f03 circuit breaker trips gate and ready pins pull low short circuit not reset reset reinitialize cb trips 0v v on 0.4v 0.76v 0.8v >v cb
ltc4213 14 4213f operating temperature of 0 to 70 c. r dson @ 25 c = 100% r dson @ 0 c = 90% r dson @ 70 c = 120% mosfet resistance variation: r dson(nom) = 15m ? 0.82 = 12.3m ? r dson(max) = 15m ? 1.333 ? 0.93 ? 1.2 = 15m ? 1.488 = 22.3m ? r dson(min) = 15m ? 0.667 ? 0.80 ? 0.90 = 15m ? 0.480 = 7.2m ? v cb variation: nom v cb = 25mv = 100% min v cb = 22.5mv = 90% max v cb = 27.5mv = 110% the current limits are: i limit(nom) = 25mv/12.3m ? = 2.03a i limit(min) = 22.5mv/22.3m ? = 1.01a i limit(max) = 27.5mv/7.2m ? = 3.82a for proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. so this system is suitable for operating load current up to 1a. from this calculation, we can start with the general rule for mosfet r dson by assuming maxi- mum operating load current is roughly half of the i limit(nom) . equation 7 shows the rule of thumb. i v r opmax cb nom dson nom = () () ? () 2 7 note that the r dson(nom) is at the ltc4213 nominal operating ? v gsmax rather than at typical vendor spec. table 1 gives the nominal operating ? v gsmax at the various operating v cc . from this table users can refer to the mosfets data sheet to obtain the r dson(nom) value. table 1. nominal operating ? v gsmax for typical bias supply voltage v cc (v) ? v gsmax (v) 2.3 4.3 2.5 5.0 2.7 5.6 3.0 6.5 3.3 7.0 5.0 7.0 6.0 7.0 load supply power-up after circuit breaker armed figure 4 shows a normal power-up sequence for the circuit in figure 1 where the v in load supply power-up after circuit breaker is armed. v cc is first powered up by an auxiliary bias supply. v cc rises above 2.07v at time point 1. v on exceeds 0.8v at time point 2. after a 60 s debounce delay, the gate pin starts ramping up at time point 3. the external mosfet starts conducting at time point 4. at time point 5, v gate exceed ? v gsarm and the circuit breaker is armed. after 50 s (t ready delay), ready pulls high by an external resistor at time point 6. ready signals the v in load supply module to start its ramp. the load supply begins soft-start ramp at time point 7. the load supply ramp rate must be slow to prevent circuit breaker tripping as in equation (8). ? ? v t ii c in opmax load load < ? () 8 where i opmax is the maximum operating current defined by equation 7. for illustration, v cb = 25mv and r dson = 3.5m ? at the nominal operating ? v gsmax . the maximum operating current is 3.5a (refer to equation 7). assuming the load can draw a current of 2a at power-up, there is a margin of 1.5a available for c load of 100 f and v in ramp rate should be <15v/ms. at time point 8, the current through the mosfet reduces after c load is fully charged. applicatio s i for atio wu u u
ltc4213 15 4213f applicatio s i for atio wu u u figure 4. load supply power-up after circuit breaker armed 0.8v 2.07v 100 a 12 3 4 5 6 7 8 v cc , v on circuit breaker arms v th ? v gsmax ? v gsmax + v sensen ? v gsarm v cb v ready v gate ? v sense reset mode normal cycle t ready startup cycle t debounce v sensep , v sensen 4213 f04
ltc4213 16 4213f applicatio s i for atio wu u u figure 5. load supply power-up before v cc v on > 0.8v v th 01 2 3 4 5 6 7 8 v cc , v on circuit breaker arms ready signals v ready v sensen v sensep reset mode normal cycle t ready startup cycle t debounce v gate 4213 f05 v sensep C v sensen = v cb v gate maxes out v cc > 2.07v ? v gsarm + v sensen ? v gsmax + v sensen load supply power-up before v cc referring back to figure 1, the v in load supply can also be powered up before v cc . figure 5 shows the timing dia- gram with the v in load supply active initially. an internal circuit ensures that the gate pin is held low. at time point 1, v cc clears uvlo and at time point 2, on clears 0.8v. 60 s later at time point 3, the gate is ramped up with 100 a. at time point 4, gate reaches the external mosfet threshold v th and v out starts to ramp up. at time point 5, v sensen is near its peak. at time point 6, the circuit breaker is armed and the circuit breaker can trip if ? v sense > v cb . at time point 7, the gate voltage peaks. 50 s after time point 6, ready goes high. startup problems there is no current limit monitoring during output charg- ing for the figure 5 power-up sequence where the load supply is powered up before v cc . this is because the gate voltage is below ? v gsarm and the mosfet may not reach the specified r dson . the v in load supply should have sufficient capability to handle the inrush as the output charges up. for proper startup, the final load at time
ltc4213 17 4213f the selected mosfet v gs absolute maximum rating should meet the ltc4213 maximum ? v gsmax of 8v. other mosfet criteria such as v bdss , i dmax , and r dson should be reviewed. spikes and ringing above maximum operating voltage should be considered when choosing v bdss . i dmax should be greater than the current limit. the maximum operating load current is determined by the r dson value. see the section on calculating current limit for details. supply requirements the ltc4213 can be powered from a single supply or dual supply system. the load supply is connected to the sensep pin and the drain of the external mosfet. in the single supply case, the v cc pin is connected to the load supply, preferably with an rc filter. with dual supplies, v cc is connected to an auxiliary bias supply v aux where v aux voltage should be greater or equal to the load supply voltage. the load supply voltage must be capable of sourcing more current than the circuit breaker limit. if the load supply current limit is below the circuit breaker trip current, the ltc4213 may not react when the output overloads. furthermore, output overloads may trigger uvlo if the load supply has foldback current limit in a single supply system. v in transient and overvoltage protection input transient spikes are commonly observed whenever the ltc4213 responds to overload. these spikes can be large in amplitude, especially given that large decoupling capacitors are absent in hot swap environments. these short spikes can be clipped with a transient suppressor of adequate voltage and power rating. in addition, the ltc4213 can detect a prolonged overvoltage condition. when applicatio s i for atio wu u u point 6 should be within the circuit breaker limits. other- wise, the system fails to start and the circuit breaker trips immediately after arming. in most applications additional external gate capacitance is not required unless c load is large and startup becomes problematic. if an external gate capacitor is employed, its capacitance value should not be excessive unless it is used with a series resistor. this is because a big gate capacitor without resistor slows down the gate turn off during a fault. an alternative method would be a stepped i sel pin to allow a higher current limit during startup. in the event of output short circuit or a severe overload, the load supply can collapse during gate ramp up due to load supply current limit. the chosen mosfet must withstand this possible brief short circuit condition before time point 6 where the circuit breaker is allowed to trip. bench short circuit evaluation is a practical verification of a reliable design. to have current limit while powering a mosfet into short circuit conditions, it is preferred that the load supply sequences to turn on after the circuit breaker is armed as described in an earlier section. power-off cycle the system can be powered off by toggling the on pin low. when on is brought below 0.76v for 5 s, the gate and ready pins are pulled low. the system resets when on is brought below 0.4v for 80 s. mosfet selection the ltc4213 is designed to be used with logic (5v) and sub-logic (3v) mosfets for v cc potentials above 2.97v with ? v gsmax exceeding 4.5v. for a v cc supply range between 2.3v and 2.97v, sub-logic mosfets should be used as the minimum ? v gsmax is less than 4.5v.
ltc4213 18 4213f applicatio s i for atio wu u u 4213 f06 + ltc4213 v cc on ready c1 10 f c load 100 f r4 10k i sel gnd gate q1 si4410dy q2 2n7002 v in v out 5v 1a sensen sensep c in 100 f r1 33 ? d1 mbro520l r3 324k r2 80.6k reset v in 5v + c2 0.22 f figure 6. single supply electronic fuse sensep exceeds v cc + 0.7v for more than 65 s, the ltc4213s internal overvoltage protection circuit acti- vates and the gate pin pulls down and turns off the external mosfet. typical electronic fuse application for a single supply system figure 6 shows a single supply electronic fuse application. an rc filter at v cc pin filters out transient spikes. an optional schottky diode can be added if severe v cc dips during a fault start-up condition is a concern. the use of the schottky and rc filter combination is allowed if the load supply is above 2.9v and the total voltage drop towards the v cc pin is less than 0.4v. the ltc4213s internal uvlo filter further rejects bias supplys transients of less than t reset . during power-up, it is good engineer- ing practice to ensure that v cc is fully established before the on pin enables the system at v on = 0.8v. in this application, the v cc voltage reached final value approxi- mately after a 5.3 ? r 1 c 1 delay. this is followed by the on pin exceeding 0.8v after a 0.17 ? r 2 c 2 delay. the gate pin starts up after an internal t debounce delay. hot swap is a trademark of linear technology corporation. typical single supply hot swap application a typical single supply hot swap application is shown in figure 7. the reset signal at the backplane is held low initially. when the pcb long edge makes contact the on pin is held low (<0.4v) and the ltc4213 is kept in reset mode. when the short edge makes contact the v in load supply is connected to the card. the v cc is biased via the rc filter. the v out is pre-charged via r5. to power-up successfully, the r5 resistor value should be small enough to provide the load requirement and to overcome the 280 a current source sinking into the sensen pin. on the other hand, the r5 resistor value should be big enough avoiding big inrush current and preventing big short circuit current. when reset signals high at backplane, c2 capacitor at the on pin charges up via the r3/r2 resistive divider. when on pin voltage exceeds 0.8v, the gate pin begins to ramp up. when the gate voltage peaks, the external mosfet is fully turned on and the v in -to-v out voltage drop reduces. in normal mode operation, the ltc4213 monitors the load current through the r dson of the external mosfet.
ltc4213 19 4213f package descriptio u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 C 0.05 (ddb8) dfn 1103 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.675 0.05 2.50 0.05 package outline 0.25 0.05 0.50 bsc pin 1 chamfer of exposed pad 0.50 bsc ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702)
ltc4213 20 4213f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/tp 0405 500 ? printed in usa related parts typical applicatio u 4213 ta02 + ltc4213 v cc on ready c2 1 f c load 100 f r4 10k r5 330 ? r3 182k i sel nc gnd gate q1 irf7455 v out 3.3v 3.6a sensen sensep zx smaj6.0a d1 bat54alt1 c1 2.2 f r1 68 ? r2 80.6k reset v in 3.3v v in backplane gnd card gnd staggered pcb edge connector figure 7. single supply hot board insertion part number description comments ltc1421 dual channel, hot swap? controller 24-pin, operates from 3v to 12v and supports C12v ltc1422 single channel, hot swap controller in so-8 operates from 2.7v to 12v, system reset output ltc1642 fault protected, hot swap controller operates up to 16.5v, overvoltage protection to 33v ltc1643al/ltc1643ah pci hot swap controllers 3.3v, 5v and 12v supplies ltc1645 dual channel hot swap controller operates from 1.2v to 12v, power sequencing ltc1647 dual channel, hot swap controller operates from 2.7v to 16.5v ltc4210 single channel, hot swap controller in sot-23 operates from 2.7v to 16.5v, multifunction current control ltc4211 single channel, hot swap controller in msop 2.5v to 16.5v, multifunction current control ltc4216 ultra low voltage hot swap controller operates from 2.7v to 16.5v, multifunction current ltc4221 dual channel, hot swap controller protects load voltages from 0v to 6v ltc4230 triple channel, hot swap controller 1.7v to 16.5v, multifunction current control ltc4251 C48v hot swap controller in s0t-23 C48v hot swap controller, active current limiting ltc4252 C48v hot swap controller in msop active current limiting with drain acceleration ltc4253 C48v hot swap controller and sequencer active current limiting with drain acceleration and three sequenced power good outputs

▲Up To Search▲

Price & Availability of LTC4213CDDB

	To Download LTC4213CDDB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .